LDO (Analog layout)

have a current requirement of 25mA in a PMOS LDO using 45nm technology. I am using 100 pass transistors, arranged in a 10×10 grid. How should I route the connections using metals M1 to M5 to achieve 25mA of current? I am using Cadence Virtuoso. Where should I stack the metal layers? Just give me your rough ideology to achive 25mA of curre